1. Field of the Invention
The present invention relates to a MOS differential amplifier circuit having linear transconductance formed on a semiconductor integrated circuit, and in particular, to a MOS linear transconductance amplifier that operates in a low voltage and is excellent in a frequency characteristic.
2. Description of the Prior Art
FIG. 8 is a circuit diagram showing a conventional MOS linear transconductance amplifier disclosed in Japanese Patent Laid-Open No. 11-251848.
This MOS linear transconductance amplifier comprises a MOS differential pair 1 formed with two n-channel MOS transistors M1 and M2 whose sources are connected with each other, and two n-channel MOS transistors M3 and M4 which operate as their load.
Sources of the MOS transistors M1 and M2 that form the MOS differential pair 1 are grounded through a constant current source 2 (current value: Iss). This MOS differential pair 1 is driven by the constant current Iss generated by the constant current source 2. Gates of the MOS transistors M1 and M2 form an input terminal pair of the amplifier concerned, and an input voltage Vi is applied between those gates. Each ratio (W/L) of gate width (W) and gate length (L) of the MOS transistors M1 and M2 is K1 as large as that of a unit MOS transistor (K1 is a constant, but K1xe2x89xa71).
The MOS transistor M3 operates as the load of the MOS transistor M1. A source of the MOS transistor M3 is connected to a drain of the MOS transistor M1, and the drain of the MOS transistor M3 is connected to a supply voltage line from which supply voltage VDD is applied, and a bias voltage (DC constant voltage) VB is applied to a gate of the MOS transistor M3.
The MOS transistor M4 operates as the load of the MOS transistor M2. A source of the MOS transistor M4 is connected to a drain of the MOS transistor M2, a drain of the MOS transistor M4 is connected to the supply voltage line from which the supply voltage VDD is applied, and the same bias voltage VB as that applied to the MOS transistor M3 is applied to a gate of the MOS transistor M4. Each ratio (W/L) of gate width (W) and gate length (L) of the MOS transistors M3 and M4 is K2 as large as that of the unit MOS transistor (K2 is a constant, however K2xe2x89xa71).
Next, the operation principle of a MOS linear transconductance amplifier shown in FIG. 8 will be described.
It is assumed that a body effect and a channel length modulation are disregarded and the relation between a drain current ID and a voltage between the gate and source of a MOS transistor which is operating in a saturation region follows a square-law. Then, the drain current ID is expressed as shown in a following formulas (1a) and (1b):   {                                                        I              D                        =                          K              ⁢                              xe2x80x83                            ⁢                                                β                  ⁡                                      (                                                                  V                        GS                                            -                                              V                        TH                                                              )                                                  2                                                                                        (                                                V                  GS                                ≥                                  V                  TH                                            )                        ⁢                          xe2x80x83                                                                                      I              D                        =            0                                                (                                          V                GS                            ≤                              V                TH                                      )                                ⁢                                                      xe2x80x83                        ⁢                          (1a)                                                                                      xe2x80x83                        ⁢                          (1a)                                          
In these formulas (1a) and (1b), a symbol K is a ratio of the ratio (W/L) of the gate width (W) and gate length (L) of the MOS transistor to that of the unit MOS transistor. In addition, a symbol xcex2 is a transconductance parameter and a symbol VTH is threshold voltage. Assuming that an effective mobility of a carrier is xcexc and a gate oxide film capacity per unit area is COX, the transconductance parameter xcex2 will be defined by xcex2=xcexc (COX/2) (W/L).
If it is assumed that characteristics of elements are almost consistent with each other, the two output currents ID1 and ID2 of the MOS differential pair 1, i.e., the drain currents of these MOS transistors M1 and M2, are expressed as shown in the following formulas (2a) and (2b), respectively.                               I          D1                =                              1            2                    ⁢                      {                                          I                0                            +                                                K                  1                                ⁢                β                ⁢                                  xe2x80x83                                ⁢                                  V                  i                                ⁢                                                                                                    2                        ⁢                                                  I                          ss                                                                                                                      K                          1                                                ⁢                        β                                                              -                                          V                      i                      2                                                                                            }                    ⁢                      (                                          "LeftBracketingBar"                                  V                  i                                "RightBracketingBar"                            ≤                                                                    I                    ss                                                                              K                      1                                        ⁢                    β                                                                        )                                              (2a)                                          I          D2                =                              1            2                    ⁢                      {                                          I                0                            -                                                K                  1                                ⁢                β                ⁢                                  xe2x80x83                                ⁢                                  V                  i                                ⁢                                                                                                    2                        ⁢                                                  I                          ss                                                                                                                      K                          1                                                ⁢                        β                                                              -                                          V                      i                      2                                                                                            }                    ⁢                      (                                          "LeftBracketingBar"                                  V                  i                                "RightBracketingBar"                            ≤                                                                    I                    ss                                                                              K                      1                                        ⁢                    β                                                                        )                                              (2b)            
As shown in formulas (2a) and (2b), an operational input voltage range of the MOS differential pair 1 is |Vi|xe2x89xa6{Iss/(K1xcex2)}.
The drain currents ID1 and ID2 of the MOS transistors M1 and M2 expressed in formulas (2a) and (2b) are converted into voltages respectively by square root (root) compression performed by the MOS transistors M3 and M4 serving as their loads. Therefore, two output voltages V01 and V02 of the MOS differential pair 1 having the MOS transistors M3 and M4 as loads are generated in the drains of the MOS transistors M1 and M2 respectively, and are expressed in the following formulas (3a) and (3b).                                           V            D1                    =                                    V              B                        -                          V              TH                        -                                                            I                  D1                                                                      K                    2                                    ⁢                  β                                                                    ⁢                  (                                    "LeftBracketingBar"                              V                i                            "RightBracketingBar"                        ≤                                                            I                  ss                                                                      K                    1                                    ⁢                  β                                                              )                                    (3a)                                                      V            D2                    =                                    V              B                        -                          V              TH                        -                                                            I                  D2                                                                      K                    2                                    ⁢                  β                                                                    ⁢                  (                                    "LeftBracketingBar"                              V                i                            "RightBracketingBar"                        ≤                                                            I                  ss                                                                      K                    1                                    ⁢                  β                                                              )                                    (3b)            
That is, when a differential output voltage of the MOS differential pair 1 is defined as xcex94V, the xcex94V is expressed as follows.                               Δ          ⁢                      xe2x80x83                    ⁢          V                =                                            V              O1                        -                          V              O2                                =                                    -                              1                                                                            K                      2                                        ⁢                    β                                                                        ⁢                          (                                                                    I                    D1                                                  -                                                      I                    D2                                                              )                                                          (        4        )            
Here, a following formula (5) is introduced. In the formula (5), symbols a and b are constants and symbol x is a variable.                               b          ⁡                      (                                                            a                  +                                                            2                                        ⁢                                          xe2x80x83                                        ⁢                    x                    ⁢                                                                  1                        -                                                                              x                            2                                                    2                                                                                                                                -                                                a                  -                                                            2                                        ⁢                    x                    ⁢                                                                  1                        -                                                                              x                            2                                                    2                                                                                                                                          )                          =                  b          ⁢                      2                    ⁢          x                                    (        5        )            
In addition, in the formula (5), these symbols a, b, and x are set up as follows.                               a          =          1                ,                  b          =                                                    I                ss                            /              2                                      ,                  x          =                                    V              i                        /                                                            I                  SS                                                                      K                    1                                    ⁢                  β                                                                                        (        6        )            
Then, the left side of the formula (5) becomes equal to what is obtained by substituting the formulas (2a) and (2b) for the formula (4). At this time, the right-hand side of the formula (5) becomes (K1xcex2)xc2x7VI. Therefore, the following formula (7) is obtained.                               Δ          ⁢                      xe2x80x83                    ⁢          V                =                                            1                                                                    K                    2                                    ⁢                  β                                                      ⁢                          (                                                                    I                    D1                                                  -                                                      I                    D2                                                              )                                =                                    1                                                                    K                    2                                    ⁢                  β                                                      ⁢                                                                                K                    1                                    ⁢                  β                                ⁢                                  xe2x80x83                                                      ⁢                                          V                i                            ⁡                              (                                                      "LeftBracketingBar"                                          V                      i                                        "RightBracketingBar"                                    ≤                                                                                    I                        SS                                                                                              K                          1                                                ⁢                        β                                                                                            )                                                                        (        7        )            
It is obvious from FIG. 7, the differential output voltage xcex94V of the MOS differential pair 1, i.e., a difference between the square roots of the drain current ID1 and drain current ID2 expressed by the formulas (2a) and (2b), respectively, is proportional to an input voltage Vi as apparent from this formula (7).
In addition, when a differential output current of the MOS differential pair 1 is defined as xcex94ID, xcex94ID is expressed like a following formula (8) with using drain currents ID1 and ID2.                                                                         Δ                ⁢                                  xe2x80x83                                ⁢                                  I                  D                                            =                                                                    I                    D1                                    -                                      I                    D2                                                  =                                                      (                                                                                            I                          D1                                                                    -                                                                        I                          D2                                                                                      )                                    ⁢                                      (                                                                                            I                          D1                                                                    +                                                                        I                          D2                                                                                      )                                                                                                                          =                                                K                  1                                ⁢                β                ⁢                                  xe2x80x83                                ⁢                                  V                  i                                ⁢                                                                                                    2                        ⁢                                                  I                          SS                                                                                                                      K                          1                                                ⁢                        β                                                              -                                          V                      i                      2                                                                      ⁢                                  (                                                            "LeftBracketingBar"                                              V                        i                                            "RightBracketingBar"                                        ≤                                                                                            I                          SS                                                                                                      K                            1                                                    ⁢                          β                                                                                                      )                                                                                        (        8        )            
Therefore, it can be seen that the differential output current xcex94ID of the MOS differential pair 1 includes a linear term shown in formula (9) and a nonlinear term shown in formula (10) as follows:                                                         I              D1                                -                                    I              D2                                      =                                                                              K                  1                                ⁢                β                            ⁢                              xe2x80x83                                              ⁢                                    V              i                        ⁡                          (                                                "LeftBracketingBar"                                      V                    i                                    "RightBracketingBar"                                ≤                                                                            I                      SS                                                                                      K                        1                                            ⁢                      β                                                                                  )                                                          (        9        )                                                                    I              D1                                +                                    I              D2                                      =                                                            K                1                            ⁢              β                                ⁢                                                                      2                  ⁢                                      I                    SS                                                                                        K                    1                                    ⁢                  β                                            -                              V                i                2                                              ⁢                      (                                          "LeftBracketingBar"                                  V                  i                                "RightBracketingBar"                            ≤                                                                    I                    SS                                                                              K                      1                                        ⁢                    β                                                                        )                                              (        10        )            
Letting the source voltage of the MOS transistors M1 and M2, which form the MOS differential pair 1 and whose sources are mutually connected, be a common source voltage VS1, the common source voltage VS1 is expressed in the following formula (11).                               V          S1                =                              V            CM1                    -                      V            TH                    -                                    1              2                        ⁢                                                                                2                    ⁢                                          I                      SS                                                                                                  K                      1                                        ⁢                    β                                                  -                                  V                  i                  2                                                                                        (        11        )            
In the formula (11), VCM1 is a common mode voltage of the input voltage Vi that is differentially inputted. As shown in the formula (11), since the common source voltage VS1 is a function of the input voltage Vi, the common source voltage VS1 is changed with an input voltage Vi. Moreover, a 3rd term (square root term) in the formula (11) is equal to a second square root portion in the nonlinear term (10) with disregarding a value of a coefficient that is a multiplier to it. Therefore, it is understood that the nonlinear term (9) of the differential output current xcex94ID in the MOS differential pair 1 originates in the change of the common source voltage VS1.
This means that, if it is possible to fix the common source voltage VS1 of the MOS differential pair 1 to a constant voltage, a linear operation of the MOS differential pair 1 can be performed. Therefore, the differential output voltage xcex94V of the MOS differential pair 1 is expressed like the following formula (12).                               Δ          ⁢                      xe2x80x83                    ⁢          V                =                                            V              O1                        -                          V              O2                                =                                    -                                                                    K                    1                                                        K                    2                                                                        ⁢                                          V                i                            (                                                "LeftBracketingBar"                                      V                    i                                    "RightBracketingBar"                                ≤                                                                            I                      SS                                                                                      K                        1                                            ⁢                      β                                                                                  "AutoRightMatch"                        ⁢                          "AutoLeftMatch"              )                                                          (        12        )            
In the formula (12), if the ratio K2 of the gate width (W) and gate length (L) of the MOS transistors M3 and M4 that serve as loads is larger than the ratio K1 of the gate width (W) and gate length (L) of the MOS transistors M1 and M2 which form the MOS differential pair 1, this MOS differential pair 1 serves as a antiphase linear attenuator. On the other hand, if K2 is equal to or smaller than K1, this MOS differential pair 1 serves as a antiphase linear amplifier. Here, its good linearity is realized over the entire operation input voltage range |Vi|xe2x89xa6{Iss/(K1xcex2)}.
As obvious from the formula (12), the differential output voltage xcex94V of the MOS differential pair 1 having the MOS transistors M3 and M4 as loads is proportional to the input voltages Vi. In other words, the MOS differential pair 1 having the MOS transistors M3 and M4 as loads operates as the linear attenuator or the linear amplifier to the input voltage Vi. Then, if (K2/K1) is set as a small value, a high gain can be realized.
In addition, when a common mode voltage of output voltages V01 and V02 is defined as VCM2, the common mode voltage VCM2 is expressed with the following formula (13).                                                                         V                CM2                            =                                                                                          V                      o1                                        +                                          V                      o2                                                        2                                =                                                      V                    B                                    -                                      V                    TH                                    -                                                                                    I                                                  D                          1                                                                                                                      K                          2                                                ⁢                        β                                                                              -                                                                                    I                        D2                                                                                              K                          2                                                ⁢                        β                                                                                                                                                                    =                                                V                  B                                -                                  V                  TH                                -                                                      1                    2                                    ⁢                                                                                    K                        1                                                                    K                        2                                                                              ⁢                                                                                                              2                          ⁢                                                      I                            SS                                                                                                                                K                            1                                                    ⁢                          β                                                                    -                                              V                        i                        2                                                                                                                                                                    =                                                V                  B                                -                                  V                  TH                                -                                                                                                    K                        1                                                                    K                        2                                                                              ⁢                                      (                                                                  V                        CM1                                            -                                              V                        TH                                            -                                              V                        S1                                                              )                                    ⁢                                      (                                                                  "LeftBracketingBar"                                                  V                          i                                                "RightBracketingBar"                                            ≤                                                                                                    I                            SS                                                                                                              K                              1                                                        ⁢                            β                                                                                                                )                                                                                                          (        13        )            
The formula (13) shows that the common mode voltage VCM2 of the output voltages V01 and V02 of the MOS differential pair 1 which have the MOS transistors M3 and M4 as loads are expressed with using the common source voltage VS1 (refer to the above-described formula (11)).
FIG. 9 is a graph showing a calculated values of the output voltage characteristic of the MOS differential pair 1 shown in FIG. 8.
In FIG. 9, two curves 31 and 32 show the output voltages V01 and V02 of the MOS differential pair 1 respectively, and a curve 33 shows the common mode voltage VCM2 of the input voltage Vi. A curve 34 shows a voltage [xe2x88x92V01+2(VBxe2x88x92VTH)], and a straight line 35 shows a voltage [V02xe2x88x92V01+VBxe2x88x92VTH]. It is obvious from straight line 35, the differential output voltage xcex94V of the MOS differential pair 1 is proportional to the input voltage Vi.
FIG. 10 is a circuit diagram showing a MOS triple-tail cell 3 used for a MOS linear transconductance amplifier (refer to FIG. 11) according to an embodiment of the present invention.
This MOS linear transconductance amplifier has a configuration of combining the MOS triple-tail cell shown in FIG. 10, and the MOS linear transconductance amplifier shown in FIG. 8. As shown in FIG. 10, this MOS triple-tail cell 3 is formed with three n-channel MOS transistors M5, M6 and M7 whose sources are connected each other. The sources of the MOS transistors M5, M6 and M7 are grounded in common through a constant current source4 (current value: I0). This MOS triple-tail cell 3 is driven by the constant current I0 generated by the constant current source 4.
Each ratio (W/L) of the gate width (W) and gate length (L) of the MOS transistors M5 and M6 are equal to that of the unit MOS transistor, respectively. A ratio (W/L) of the gate width (W) and gate length (L) of the MOS transistor M7 is K3 times as large as that of the unit MOS transistor (K3 is a constant, however K3xe2x89xa71).
The first output voltage V01 of the MOS differential pair 1 generated in the drain of the MOS transistor M1 forming the MOS differential pair 1 (namely, the MOS linear transconductance amplifier in FIG. 8) is applied to the gate of the MOS transistor M5. At the same time, the second output voltage V02 of the MOS differential pair 1 generated in the drain of MOS transistor M2 forming the MOS differential pair 1 is applied to the gate of MOS transistor M6. The Difference (namely, differential output voltage of the MOS differential pair) xcex94V between these two output voltages V01 and V02 becomes the input voltage of the triple-tail cell 3.
A drain of the MOS transistor M7 is connected to a supply voltage line (VDD), and a control voltage (DC constant voltage) Vc is applied to its gate. Two drains of the MOS transistors M5 and M6 forms an output terminal pair of this triple-tail cell 3, and output currents I+ and Ixe2x88x92 are taken out from the output terminal pair, respectively. An n-channel MOS transistor M8 and a constant current source 5 (current value: Iss/2) constitute a control voltage generating circuit for generating the control voltage Vc for the MOS transistor M7. A source of the MOS transistor M8 is grounded through the constant current source 5, a drain of the MOS transistor M8 is connected to a supply voltage line (VDD), and a bias voltage VB is applied to its gate.
Next, an operation principle of this MOS triple-tail cell 3 will be described.
A MOS quadritail cell consists of the unit transistors M5 and M6 and the transistors M7 and M8. Here, transistor size ratios of the transistors M7 and M8 to the unit transistor are K3, and the sources of the transistors M5 to M7 are commonly connected and are driven by the constant current I0. When a voltage xcex94V is applied between the gates of the transistors M5 and M6, and a voltage Vc is applied to the gate of the transistor M7, and VCM3 is input common mode voltage, the drain currents of respective transistors are expressed as follows:
ID5=xcex2(VCM3+xcex94V/2xe2x88x92VS2xe2x88x92VTH)2xe2x80x83xe2x80x83(14) 
ID6xe2x88x92xcex2(VCM3xe2x88x92xcex94V/2xe2x88x92VS2xe2x88x92VTH)2xe2x80x83xe2x80x83(15) 
ID7=ID8=K3xcex2(VCM3+VCxe2x88x92VS2xe2x88x92VTH)2xe2x80x83xe2x80x83(16) 
where an input common mode voltage is made to be VCM3. Here, a symbol VS2 is a common source voltage of the MOS quadritail cell.
Moreover, the following formula is obtained from a condition of the tail current:
ID5+ID6+ID7+ID8=I0xe2x80x83xe2x80x83(17) 
With solving formula (VCM3xe2x88x92VS2xe2x88x92VTH) by substituting the formulas (14) to (16) for the formula (17), the solution is as follows:                                           V            CM3                    -                      V            S2                    -                      V            TH                          =                                                            -                                  K                  3                                            ⁢                              V                C                                      +                                                                                (                                                                  K                        3                                            +                      1                                        )                                    ⁢                                                            I                      0                                                              2                      ⁢                      β                                                                      -                                                                                                    K                        3                                            +                      1                                        4                                    ⁢                                                            (                                              Δ                        ⁢                                                  xe2x80x83                                                ⁢                        V                                            )                                        2                                                  -                                                      K                    3                                    ⁢                                      V                    C                    2                                                                                                          K              3                        +            1                                              (        18        )            
When the drain currents of MOS transistors M5 and M6 are defied as ID5 and ID6 respectively, a differential output current xcex94I (=I+xe2x88x92Ixe2x88x92) of this triple-tail cell 3 is expressed in the following formula (19).                                                                         Δ                ⁢                                  xe2x80x83                                ⁢                I                            =                              xe2x80x83                            ⁢                                                                    U                    D5                                    -                                      I                    D6                                                  =                                  2                  ⁢                  β                  ⁢                                      xe2x80x83                                    ⁢                                      (                                          Δ                      ⁢                                              xe2x80x83                                            ⁢                      V                                        )                                    ⁢                                      xe2x80x83                                    ⁢                                      (                                                                  V                        CM3                                            -                                              V                        S2                                            -                                              V                        TH                                                              )                                                                                                                          =                              xe2x80x83                            ⁢                                                                                                                                                                        -                            2                                                    ⁢                                                      K                            3                                                    ⁢                                                      β                            ⁡                                                          (                                                              Δ                                ⁢                                                                  xe2x80x83                                                                ⁢                                V                                                            )                                                                                ⁢                                                      V                            C                                                                          +                                                                                                                                                2                        ⁢                                                  β                          ⁡                                                      (                                                          Δ                              ⁢                                                              xe2x80x83                                                            ⁢                              V                                                        )                                                                          ⁢                                                                                                                                            (                                                                                                      K                                    3                                                                    +                                  2                                                                )                                                            ⁢                                                                                                I                                  0                                                                β                                                                                      -                                                                                                                                                                K                                    3                                                                    +                                  2                                                                2                                                            ⁢                                                                                                (                                                                      Δ                                    ⁢                                                                          xe2x80x83                                                                        ⁢                                    V                                                                    )                                                                2                                                                                      -                                                          2                              ⁢                                                              K                                3                                                            ⁢                                                              V                                C                                2                                                                                                                                                                                                                                              K                    3                                    +                  2                                                                                                                        xe2x80x83                            ⁢                              (                                                      "LeftBracketingBar"                                          Δ                      ⁢                                              xe2x80x83                                            ⁢                      V                                        "RightBracketingBar"                                    ≤                                      min                    ⁢                                          {                                                                                                                                                                  2                                ⁢                                                                  I                                  0                                                                                            β                                                        -                                                          4                              ⁢                                                              V                                C                                2                                                                                                                                    ,                                                                                                                                                                                                                                                        -                                      2                                                                        ⁢                                                                          K                                      3                                                                        ⁢                                                                          V                                      C                                                                                                        +                                                                                                                                                                                                                      2                                  ⁢                                                                                                                                                                                              (                                                                                                                                    K                                              3                                                                                        +                                            4                                                                                    )                                                                                ⁢                                                                                                                              I                                            0                                                                                    β                                                                                                                    -                                                                              4                                        ⁢                                                                                  xe2x80x83                                                                                ⁢                                                                                  K                                          3                                                                                ⁢                                                                                  V                                          C                                          2                                                                                                                                                                                                                                                                                                                                                            K                              3                                                        +                            4                                                                                              }                                                                      )                                                                        (        19        )            
Here, the differential output voltage xcex94V of the MOS differential pair 1 that is inputted between the gates of the MOS transistors M5 and M6 is linear to the input voltage Vi inputted to the MOS differential pair 1 (that is, this amplifier). Moreover, the drain currents ID5 and ID6 of the MOS transistors M5 and M6 which form the triple-tail cell 3 have a square-law characteristics to the input voltage xcex94V inputted to the triple-tail cell 3, respectively. In consideration of these, in order that the amplifier shown in FIG. 8 outputs a current having the square-law characteristics, it is necessary that the differential output current xcex94I of this triple-tail cell 3 that is expressed in the formula (19) becomes linear to the input voltage xcex94V, i.e., that the differential output current xcex94I is proportional to the input voltage xcex94V.
That is, when c is constant, it is required that satisfying a following formula:
xcex94I=cxcex94Vxe2x80x83xe2x80x83(20) 
Therefore, a coefficient multiplied to xcex94V of numerator of the above-described formula (19) must be equal to a constant c. In other words, it is necessary to satisfy a following formula (21).                                                         -                              K                3                                      ⁢                          V              C                                +                                                                      (                                                            K                      3                                        +                    2                                    )                                ⁢                                                      I                    0                                                        2                    ⁢                    β                                                              -                                                                                          K                      3                                        +                    2                                    4                                ⁢                                                      (                                          Δ                      ⁢                                              xe2x80x83                                            ⁢                      V                                        )                                    2                                            -                              2                ⁢                                  K                  3                                ⁢                                  V                  C                  2                                                                    =                  c          ⁡                      (            constant            )                                              (        21        )            
Here, the differential output current xcex94I of the triple-tail cell 3 is as follows.                               Δ          ⁢                      xe2x80x83                    ⁢          I                =                                            2              ⁢              cβ                                                      K                3                            +              2                                ⁢                      (                          Δ              ⁢                              xe2x80x83                            ⁢              V                        )                                              (        22        )            
Moreover, with determining the control voltage Vc at this time based on the formula (21), the control voltage Vc is expressed as a following formula (23).                               V          C                =                                                            -                                  K                  3                                            ⁢              c                        +                                                                                                                              K                        3                                            ⁡                                              (                                                                              K                            3                                                    +                          2                                                )                                                              2                                    ⁢                                                            I                      0                                        β                                                  -                                                                                                                              K                          3                                                ⁡                                                  (                                                                                    K                              3                                                        +                            2                                                    )                                                                    2                                        2                                    ⁢                                                            (                                              Δ                        ⁢                                                  xe2x80x83                                                ⁢                        V                                            )                                        2                                                  -                                  2                  ⁢                                      K                    3                                    ⁢                                      c                    2                                                                                                          K              3                        ⁡                          (                                                K                  3                                +                2                            )                                                          (        23        )            
Therefore, the differential output current xcex94I of this triple-tail cell 3 expressed in the above-described formula (19) is linear to the input voltage xcex94V. That is, in order that the MOS linear transconductance amplifier shown in FIG. 8 outputs a current having a linear characteristics, the control voltage Vc must be set up so as to satisfy the formula (21). Then, the differential output current xcex94I of the triple-tail cell 3 at that time is expressed in the above-described formula (22).
For example, when defining C2 as follows:                               c          2                =                                            (                                                K                  3                                +                2                            )                        2                    ⁢                                    I              0                                      4              ⁢              β                                                          (        24        )            
the control voltage Vc is required to be set as follows:                               V          C                =                                            -                              1                2                                      ⁢                                                            I                  0                                β                                              +                                                                      I                  0                                                  2                  ⁢                                      K                    3                                    ⁢                  β                                            -                                                1                                      2                    ⁢                                          K                      3                                                                      ⁢                                                      (                                          Δ                      ⁢                                              xe2x80x83                                            ⁢                      V                                        )                                    2                                                                                        (        25        )            
As described above, if the control voltage Vc to the MOS transistor M7 of the triple-tail cell 3 is set up so as to satisfy the above-described formula (23), the differential output current xcex94I of this triple-tail cell 3 expressed in the above-described formula (19) becomes linear to the input voltage xcex94V. Thus, the differential output current xcex94I is expressed in the above-described formula (22).
FIG. 11 is a circuit diagram showing a MOS linear transconductance amplifier obtained in this way.
In this amplifier, a cascade connection of the MOS triple-tail cell 3 shown in FIG. 10 is performed to an output terminal of the MOS differential pair 1 (namely, MOS linear transconductance amplifier shown in FIG. 8) which consists of the MOS transistors M1 and M2, and MOS transistors M3 and M4 used as loads thereof. For this reason, respective gate voltages of the MOS transistors M5, M6 and M7 which form the triple-tail cell 3 become V01, V02 and (VCM2+Vc). If the gate voltage (VCM2+Vc)=VG7 of the MOS transistor M7 becomes a constant value, a gate bias circuit for generating the control voltage Vc can be simplified remarkably. Thereat, next, conditions necessary for it will be obtained.
Since the common mode voltage VCM2 of the output voltages V01 and V02 is expressed in the above-described formula (13) and the control voltage Vc is expressed as the above-described formula (23), the gate voltage VG7=(VCM2+Vc) of the MOS transistor M7 is expressed in the following formula (26). Here, symbol d is a constant.                                                                         V                G7                            =                              xe2x80x83                            ⁢                                                V                  CM2                                +                                  V                  C                                                                                                        =                              xe2x80x83                            ⁢                                                V                  B                                -                                  V                  TH                                -                                                      1                    2                                    ⁢                                                                                    K                        1                                                                    K                        2                                                                              ⁢                                                                                                              2                          ⁢                                                      I                            SS                                                                                                                                K                            1                                                    ⁢                          β                                                                    -                                              V                        i                        2                                                                                            +                                                                                                        xe2x80x83                            ⁢                                                                                          -                                              K                        3                                                              ⁢                    c                                    +                                                                                                                                                                        K                              3                                                        ⁡                                                          (                                                                                                K                                  3                                                                +                                2                                                            )                                                                                2                                                ⁢                                                                              I                            0                                                    β                                                                    -                                                                                                                                  K                              1                                                        ⁢                                                                                                                            K                                  3                                                                ⁡                                                                  (                                                                                                            K                                      3                                                                        +                                    2                                                                    )                                                                                            2                                                                                                            2                            ⁢                                                          K                              2                                                                                                      ⁢                                                                              (                                                          Δ                              ⁢                                                              xe2x80x83                                                            ⁢                              V                                                        )                                                    2                                                                    -                                              2                        ⁢                                                  K                          3                                                ⁢                                                  c                          2                                                                                                                                                          K                    3                                    (                                                            K                      3                                        +                    2                                    )                                                                                                        =                              xe2x80x83                            ⁢                              d                ⁡                                  (                  constant                  )                                                                                        (        26        )            
As mentioned above, it is required for the differential output current xcex94I of the triple-tail cell 3 to be proportional to the input voltage xcex94V in order that the MOS linear transconductance amplifier of FIG. 11 outputs the current having linear characteristics. Therefore, in the formula (26), all coefficients of the term containing the input voltage xcex94V must be zero. That is, the formula (26) must be simplified like the following formula (27).                                           V            CM2                    +                      V            C                          =                                            V              B                        -                          V              TH                        -                          c                                                K                  3                                +                2                                              =                      d            ⁡                          (              constant              )                                                          (        27        )            
Necessary conditions for satisfying the formula (27) are that satisfying two relational expressions (28a) and (28b) in the formula (26).
K3=2xe2x80x83xe2x80x83(28a)                                           I            0                    β                =                                            I              SS                                                      K                2                            ⁢              β                                +                                    c              2                        8                                              (28b)            
Therefore, when values such as current values I0 and Iss are set up so as to satisfy such relational expressions (28a) and (28b), satisfying the formula (27) and the gate voltage VG7=(VCM2+Vc) of the MOS transistor M7 becomes a constant value. Consequently, the bias circuit for generating the control voltage Vc applied to the MOS transistor M7 is remarkably simplified as shown in FIG. 11. Then, in that case, since the control voltage Vc follows the above-described formula (23) in the circuit configuration shown in FIG. 11, the differential output current xcex94I of this triple-tail cell 3 becomes linear to the input voltage xcex94V as expressed in the above-described formula (22).
Moreover, as mentioned above, the input voltage xcex94V to the MOS triple-tail cell 3 is the differential output voltage xcex94V of the MOS differential pair 1 having the MOS transistors M3 and M4 as loads, and is proportional to the input voltage Vi to this amplifier concerned. In this way, it is assured that the amplifier in FIG. 11 outputs the output current xcex94I having linear characteristics to the input voltage Vi as the differential output current xcex94I of the MOS triple-tail cell 3.
Next, an operational input voltage range of the MOS linear transconductance amplifier shown in FIG. 11 will be described.
The drain currents ID5, ID6 and ID7 of the MOS transistors M5, M6 and M7 which form the triple-tail cell 3 are expressed in regard to the input voltage xcex94V in the following formulas (29a), (29b) and (29c), respectively.                               I          D5                =                              β            4                    ⁢                                    (                                                Δ                  ⁢                                      xe2x80x83                                    ⁢                  V                                -                                                                            I                      0                                        β                                                              )                        2                    ⁢                      (                                          "LeftBracketingBar"                                  Δ                  ⁢                                      xe2x80x83                                    ⁢                  V                                "RightBracketingBar"                            ≤                                                                    I                    0                                                        2                    ⁢                    β                                                                        )                                              (29a)                                          I          D6                =                              β            4                    ⁢                                    (                                                Δ                  ⁢                                      xe2x80x83                                    ⁢                  V                                +                                                                            I                      0                                        β                                                              )                        2                    ⁢                      (                                          "LeftBracketingBar"                                  Δ                  ⁢                                      xe2x80x83                                    ⁢                  V                                "RightBracketingBar"                            ≤                                                                    I                    0                                                        2                    ⁢                    β                                                                        )                                              (29b)                                          I          D7                =                              1            2                    ⁢                      {                                          I                0                            -                                                β                  ⁡                                      (                                          Δ                      ⁢                                              xe2x80x83                                            ⁢                      V                                        )                                                  2                                      }                    ⁢                      (                                          "LeftBracketingBar"                                  Δ                  ⁢                                      xe2x80x83                                    ⁢                  V                                "RightBracketingBar"                            ≤                                                                    I                    0                                                        2                    ⁢                    β                                                                        )                                              (29c)            
Therefore, an effective tail current of two transistors that constitute a differential pair of a quadri-tail cell is shown as a following formula (30).                                           I            D5                    +                      I            D6                          =                              1            2                    ⁢                      {                                          I                0                            +                                                β                  ⁡                                      (                                          Δ                      ⁢                                              xe2x80x83                                            ⁢                      V                                        )                                                  2                                      }                    ⁢                      (                                          "LeftBracketingBar"                                  Δ                  ⁢                                      xe2x80x83                                    ⁢                  V                                "RightBracketingBar"                            ≤                                                                    I                    0                                                        2                    ⁢                    β                                                                        )                                              (        30        )            
It is obvious from the formulas (29c) and (30), a sum current of two output currents I+ and Ixe2x88x92 of the triple-tail cell 3 and ID7 are proportional to the square value of the input voltage xcex94V respectively, the sum current of those output currents I+ and Ixe2x88x92 are equiphase square currents, and ID7 shows the square current in an antiphase.
Next, the conditions that the linear input voltage range of the MOS triple-tail cell 3 and the operational input voltage range of the MOS differential pair 1 become equal will be obtained.
First, if Vi is zero in the formula (28b), the formula (27) is satisfied also in the case of Vo=0. At this time, formulas (31) and (32) are obtained.                     d        =                              V            B                    -                      V            TH                    -                                                    I                SS                                            2                ⁢                                  K                  2                                ⁢                β                                                                        (        31        )                                c        =                              4            ⁢                                                            I                  SS                                                  2                  ⁢                                      K                    2                                    ⁢                  β                                                              =                      2            ⁢                                                            2                  ⁢                                      I                    SS                                                                                        K                    2                                    ⁢                  β                                                                                        (        32        )            
Moreover, a following formula (33) is obtained by substituting the formula (32) for the formula (28b) and solving this.                               I          0                =                  2          ⁢                                    I              SS                                      K              2                                                          (        33        )            
In the case of K1=K2=1, K3=2 and Iss=I0/2, the circuit configuration shown in FIG. 11 can be most simplified. At this time, a value of the constant c can be calculated from formula (34).                     c        =                  2          ⁢                                                    I                0                            β                                                          (        34        )            
Moreover, the constant d and the control voltage Vc at this time become as shown in a following formulas (35) and (36), respectively.                     d        =                                            V              CM2                        +                          V              C                                =                                    V              B                        -                          V              TH                        -                          2              ⁢                                                                    I                    0                                    β                                                                                        (        35        )                                          V          C                =                              1            2                    ⁢                      {                                          -                                                                            I                      0                                        β                                                              +                                                                                          I                      0                                        β                                    -                                                            (                                              Δ                        ⁢                                                  xe2x80x83                                                ⁢                        V                                            )                                        2                                                                        }                                              (        36        )            
At this time, the differential output current xcex94I of the linear transconductance amplifier shown in FIG. 11 is expressed in formula (37).                               Δ          ⁢                      xe2x80x83                    ⁢          I                =                                            I              D5                        -                          I              D6                                =                                    -                                                β                  ⁢                                      xe2x80x83                                    ⁢                                      I                    0                                                                        ⁢                                          V                i                            ⁡                              (                                                      "LeftBracketingBar"                                          V                      i                                        "RightBracketingBar"                                    ≤                                                                                    I                        0                                                                    2                        ⁢                        β                                                                                            )                                                                        (        37        )            
At this time, an operation range |Vi|xe2x89xa6(I0/xcex2) becomes equal to the operation range of the MOS differential pair having transistors as loads. A transconductance is expressed in formula (38).                                           ⅆ                          (                              Δ                ⁢                                  xe2x80x83                                ⁢                V                            )                                            ⅆ                          xe2x80x83                        ⁢                          V              i                                      =                              -                                          β                ⁢                                  xe2x80x83                                ⁢                                  I                  0                                                              ⁢                      (                                          "LeftBracketingBar"                                  V                  i                                "RightBracketingBar"                            ≤                                                                    I                    0                                                        2                    ⁢                    β                                                                        )                                              (        38        )            
The MOS transistor M7 constituting the triple-tail cell 3 shown in FIG. 10 has a ratio (W/L) between the gate width (W) and gate length (L) that is two times of the ratio of the unit MOS transistor (K3=2). Therefore, the MOS transistor M7 can be divided into two unit MOS transistors M7A and M7B all of whose sources, drains and gates are connected each other. Thus, the triple-tail cell 3 can be modified into a quadri-tail cell 3xe2x80x2 shown in FIG. 12. Here, sources of the MOS transistors M7A and M7B of the quadritail cell 3xe2x80x2 are connected to each source of the MOS transistors M5 and M6, respectively. In addition, two resistors (not shown) having resistances each are RL are added as loads of the MOS transistors M5 and M6. Thus, the amplifier performs class A operation. This will be described with using FIG. 11.
FIG. 13 is a graph showing a characteristics of drain currents ID5, ID6, ID7A and ID7B of the MOS transistors M5, M6, M7A and M7B constiting the quadri-tail cell 3xe2x80x2.
In FIG. 13, curves 51, 52 and 53 show that each of the drain currents ID5, ID6, ID7A and ID7B has square-law characteristics. Moreover, a curve 54 shows that a sum of the drain currents ID7A and ID7B also has the square-law characteristics. Furthermore, it can be also seen from a curve 55 shows that a sum of the drain currents ID5 and ID7A has linear characteristics, and also from a curve 56 that a sum of drain currents ID6 and ID7B has linear characteristics. In this way, the differential output current xcex94I in the linear transconductance amplifier is converted into a voltage, which is taken out as the differential output voltage xcex94Vo.
It is obvious from FIG. 13, it can be seen from the curve 55 that the sum of the drain currents ID5 and ID7A has linear characteristics, and from the curve 56 that the sum of the drain currents ID6 and ID7B has linear characteristics. Hence, in the amplifier according to this fifth embodiment, the differential output current xcex94I can be expressed as xcex94I=(ID5+ID7A)xe2x88x92(ID6+ID7B) and this also becomes linear in a wide input voltage range |Vi|xe2x89xa6(I0/2xcex2). Therefore, the differential output voltage Vo obtained by performing the voltage conversion of the differential output current xcex94I by the resistors also has linear characteristic in a wide input voltage range |Vi|xe2x89xa6(I0/2xcex2).
FIG. 14 is a graph showing the calculated values of transfer characteristics of the MOS linear transconductance amplifier shown in FIG. 12 are shown.
In FIG. 14, two curves 81 and 82 show changes of the output currents (ID6+ID7B) and (ID5+ID7A) in the MOS linear transconductance amplifier shown in FIG. 12. FIG. 14 shows that the output currents (ID6+ID7B) and (ID5+ID7A) in the MOS linear transconductance amplifier have the linear characteristics.
Otherwise, this kind of MOS linear transconductance amplifier is described in Japanese Patent Laid-Open No. 10-209781. This circuit is shown in FIG. 15. Although an operation of this circuit is analyzed in preferred embodiments in the above-described Japanese Patent Laid-Open No. 10-209781 using formulas. However, each formula does not have a middle voltage VCM. Therefore, it is difficult to understand the operation. Moreover, since an operational input voltage range and a linear input voltage range are not shown and it is also not shown why the linear input voltage range is wide or how the linear input voltage range can be extended, technical disclosure is not sufficient.
Then, the present inventor will simply show these by performing a circuit analysis. In this circuit, since all transistors M1 to M9 are the same transistors, the circuit analysis becomes simpler by several steps than that in the case of being Japanese Patent Laid-Open No. 11-251848. In FIG. 15, the transistors M5 to M9 are mutually connected at their sources, and are driven by a constant current source 5Iss.
ID5+ID6+ID7+ID8+ID9=5ISSxe2x80x83xe2x80x83(39) 
Moreover, a current flowing in the transistor M5 drives four transistors M5 to M8 whose drains are mutually connected through a 1:4 current mirror circuit consisting of transistors M14 to M18.
Thus, the following formula is obtained:
ID5+ID6+ID7+ID8=4ID9xe2x80x83xe2x80x83(40) 
Hence, solving the formulas (39) and (40), the following formulas can be obtained:
ID5=xcex2(VCMxe2x88x92Vn2xe2x88x92VTH)2=ISSxe2x80x83xe2x80x83(41) 
ID5+ID6+ID7+ID8=4ISSxe2x80x83xe2x80x83(42) 
However, Vn2 denotes a common source voltage.
From the formula (41), the following formula can be obtained:                                           V            CM                    -                      V            n2                    -                      V            TH                          =                                            I              SS                        β                                              (        43        )            
Moreover, satisfy the following formulas:                               I          D5                =                              β            ⁡                          (                                                V                  CM                                +                                                      V                    i                                    2                                -                                  V                  n2                                -                                  V                  TH                                            )                                2                                    (        44        )                                          I          D6                =                              β            ⁡                          (                                                V                  CM                                -                                                      V                    i                                    2                                -                                  V                  n2                                -                                  V                  TH                                            )                                2                                    (        45        )            xe2x80x83ID7=ID8=xcex2(VCONTxe2x88x92Vn2xe2x88x92VTH)2xe2x80x83xe2x80x83(46)
Hence, with substituting the formulas (44) to (46) for the formula (42) and rewriting the formula (42) with using the formula (43), the following formula can be obtained:                                           V            CONT                    -                      V            CM                          =                              -                                                            I                  SS                                β                                              +                                                                                          I                    SS                                    β                                -                                                      V                    i                    2                                    4                                                      ⁢                          xe2x80x83                        ⁢                          (                                                "LeftBracketingBar"                                      V                    i                                    "RightBracketingBar"                                ≤                                                                            2                      ⁢                                              I                        SS                                                              β                                                              )                                                          (        47        )            
The input operation range where the formula (47) can be obtained is given from the following condition in which no transistors M5 to M9 become pinch-off:   (                              I          SS                          2          ⁢          β                      ≤                                                      I              SS                        β                    -                                    V              i              2                        4                              ⁢              xe2x80x83            ⁢              (                  ≤                                                    I                SS                            β                                      )              )
With substituting the formulas (43) and (47) for the formulas (44) to (46), the followings can be obtained:                               I          D5                =                                            β              4                        ⁢                          V              i              2                                +                                                    β                ⁢                                  xe2x80x83                                ⁢                                  I                  SS                                                      ⁢                          V              i                                +                                    I              SS                        ⁢                          xe2x80x83                        ⁢                          (                                                "LeftBracketingBar"                                      V                    i                                    "RightBracketingBar"                                ≤                                                                            2                      ⁢                                              I                        SS                                                              β                                                              )                                                          (        48        )                                          I          D6                =                                            β              4                        ⁢                          V              i              2                                -                                                    β                ⁢                                  xe2x80x83                                ⁢                                  I                  SS                                                      ⁢                          V              i                                +                                    I              SS                        ⁢                          xe2x80x83                        ⁢                          (                                                "LeftBracketingBar"                                      V                    i                                    "RightBracketingBar"                                ≤                                                                            2                      ⁢                                              I                        SS                                                              β                                                              )                                                          (        49        )                                          I          D7                =                              I            D8                    =                                    I              SS                        -                                          β                4                            ⁢                              V                i                2                            ⁢                              xe2x80x83                            ⁢                              (                                                      "LeftBracketingBar"                                          V                      i                                        "RightBracketingBar"                                    ≤                                                                                    2                        ⁢                                                  I                          SS                                                                    β                                                                      )                                                                        (        50        )            
Hence, the following formulas can be obtained:                                           I            D5                    +                      I            D7                          =                              2            ⁢                          I              SS                                +                                                    β                ⁢                                  xe2x80x83                                ⁢                                  I                  SS                                                      ⁢                          V              i                        ⁢                          xe2x80x83                        ⁢                          (                                                "LeftBracketingBar"                                      V                    i                                    "RightBracketingBar"                                ≤                                                                            2                      ⁢                                              I                        SS                                                              β                                                              )                                                          (        51        )                                                      I            D6                    +                      I            D8                          =                              2            ⁢                          I              SS                                -                                                    β                ⁢                                  xe2x80x83                                ⁢                                  I                  SS                                                      ⁢                          V              i                        ⁢                          xe2x80x83                        ⁢                          (                                                "LeftBracketingBar"                                      V                    i                                    "RightBracketingBar"                                ≤                                                                            2                      ⁢                                              I                        SS                                                              β                                                              )                                                          (        52        )            
Thus, both ID5+ID7 and ID6+ID5 are linear differential currents.
Here, a control voltage generating circuit consisting of the transistors M5 to M9 will be compared to an output circuit consisting of transistors M1 to M4. Supposing that the constant current Iss is removed since the current always flows in the transistor M5, it can be seen that the transistors M1 to M4 and transistors M5 to M8 have mutually equal bias conditions.
Hence, the following formulas can be obtained:                                           I            D1                    +                      I            D3                          =                              2            ⁢                          I              SS                                +                                                    β                ⁢                                  xe2x80x83                                ⁢                                  I                  SS                                                      ⁢                          V              i                        ⁢                          xe2x80x83                        ⁢                          (                                                "LeftBracketingBar"                                      V                    i                                    "RightBracketingBar"                                ≤                                                                            2                      ⁢                                              I                        SS                                                              β                                                              )                                                          (        53        )                                                      I            D2                    +                      I            D4                          =                              2            ⁢                          I              SS                                -                                                    β                ⁢                                  xe2x80x83                                ⁢                                  I                  SS                                                      ⁢                          V              i                        ⁢                          xe2x80x83                        ⁢                          (                                                "LeftBracketingBar"                                      V                    i                                    "RightBracketingBar"                                ≤                                                                            2                      ⁢                                              I                        SS                                                              β                                                              )                                                          (        54        )            
Both ID1+ID3 and ID2+ID4 are linear differential currents. That is, two output currents are expressed as follows:                               I          On                =                              -                                          β                ⁢                                  xe2x80x83                                ⁢                                  I                  SS                                                              ⁢                      V            i                    ⁢                      xe2x80x83                    ⁢                      (                                          "LeftBracketingBar"                                  V                  i                                "RightBracketingBar"                            ≤                                                                    2                    ⁢                                          I                      SS                                                        β                                                      )                                              (        55        )                                          I          Op                =                              +                                          β                ⁢                                  xe2x80x83                                ⁢                                  I                  SS                                                              ⁢                      V            i                    ⁢                      xe2x80x83                    ⁢                      (                                          "LeftBracketingBar"                                  V                  i                                "RightBracketingBar"                            ≤                                                                    2                    ⁢                                          I                      SS                                                        β                                                      )                                              (        56        )            
Hence, a linear OTA is realizable.
However, since the conventional MOS linear transconductance amplifier described above reverses a voltage with the antiphase amplifier, it is not able to lower a power supply voltage in order to maintain a linear operating input voltage. Alternatively, there is a disadvantage that, even if it is possible to lower the voltage, a circuit current in the control voltage generating circuit becomes larger than a circuit current in the main output circuit.
In analog signal processing, a differential amplifier circuit is an essential function block. In particular, a demand of a linear MOS differential amplifier circuit has increased further. Therefore, an object of the present invention is to provide a MOS linear transconductance amplifier that can be realized with an LSI and has the linear transconductance excellent in the frequency characteristic.
A MOS linear transconductance amplifier according to claim 1 is characterized in: that gates of first and second transistors whose sources are grounded form an input pair, to which a differential voltage is inputted; that a gate and drain of a third transistor are mutually connected; that drains of the above first, second and third transistors are mutually connected and are driven by a constant current; wherein the MOS linear transconductance amplifier comprises means for adding a current flowing in the above-described first transistor to a current that is a half of a current flowing in the above-described third transistor, and means for adding a current flowing in the above-described second transistor, and a current that is a half of a current flowing in the above-described third transistor; and that these two sum currents are made to be a differential output current.
A MOS linear transconductance amplifier according to claim 2 is characterized in: that gates of first and second transistors whose sources are grounded form an input pair, to which a differential voltage is inputted; that the gate and drain of a third transistor are mutually connected; that drains of the above-described first, second and third transistors are mutually connected and are driven by a constant current; that a fourth transistor whose gate is mutually connected to the gate of the above-described first transistor, a fifth transistor whose gate is mutually connected to the gate of the above-described second transistor, and sixth and seventh transistors whose gates are mutually connected to the gate of the third transistor are mutually connected at sources and are driven by a constant current; that drains of the above-described fourth transistor and above-described sixth transistor are mutually connected and form one of a differential output pair; that drains of the above-described fifth transistor and above-described seventh transistor are mutually connected, and form the other of the differential output pair; and that each gate ratio (W/L) of the above-described sixth and seventh transistors is a half of a gate ratio (W/L) of the above-described third transistor.
A MOS linear transconductance amplifier according to claim 3 is characterized in that, in the MOS linear transconductance amplifier according to claim 2, sources of the above-described first, second and third transistors are mutually connected and are grounded through a resister or a diode that is formed by mutually connecting a gate and a source.
A MOS linear transconductance amplifier according to claim 4 is characterized in: that the MOS linear transconductance amplifier comprises first, second, third and forth transistors whose sources are mutually connected, and which are driven by a constant current; that a common voltage VCM of a differential input voltage is applied to the gate of the above-described first transistor; that gates of the above-described second and third transistors constitute an input pair, to which a differential voltage is inputted; that the gate and drain of the above-described fourth transistor are mutually connected; that the above-described second, third and fourth transistors are mutually connected at their drains and are driven by a constant current; that a fifth transistor whose gate is mutually connected to the gate of the above-described second transistor, a sixth transistor whose gate is mutually connected to the gate of the above-described third transistor, and seventh and eighth transistors whose gates are mutually connected to the gate of the fourth transistor are mutually connected at their sources and are driven by a constant current; that drains of the above-described fifth transistor and above-described seventh transistor are mutually connected and form one of a differential output pair; that drains of the above-described sixth transistor and above-described eighth transistor are mutually connected, and form the other of the differential output pair; and that each gate ratio (W/L) of the above-described seventh and eighth transistors is a half of a gate ratio (W/L) of the above-described fourth transistor.
A MOS linear transconductance amplifier according to claim 5 is characterized in that, in the MOS linear transconductance amplifier according to claim 4, wherein a current flowing in the above-described first transistor is a reference current, currents having predetermined mirror ratios are supplied to the common drain of the above-described second, third and fourth transistors, and one and the other of the above-described differential output pair respectively.
A MOS linear transconductance amplifier according to claim 6 or 7 is characterized in that, in the MOS linear transconductance amplifier according to claim 4 or 5, a common source voltage of the above-described first, second, third and fourth transistors is different from a common source voltage of the above-described fifth, sixth, seventh and eighth transistors.
A MOS linear transconductance amplifier according to claim 8 or 9 is characterized in that, in the MOS linear transconductance amplifier according to claim 4 or 5, sources of the above-described first, second, third, fourth, fifth, sixth, seventh and eighth transistors are mutually connected.
Next, in other words, the configuration of the MOS linear transconductance amplifier according to the present invention will be described once again. In the MOS linear transconductance amplifier according to the present invention, that gates of the first and second transistors whose sources are grounded constitute the input pair, the differential voltage is inputted to the input pair, and the gate and drain of the third transistor is mutually connected, the above-described first, second and third transistors are mutually connected at their drains, and are driven by the constant current. Furthermore, the MOS linear transconductance amplifier comprises means for adding a current flowing in the above-described first transistor to a current that is a half of a current flowing in the above-described third transistor, and means for adding the current flowing in the above-described second transistor to the current that is a half of the current flowing in the above-described third transistor, and these two sum currents are made to be differential output currents.
Alternatively, sources of the above-described first, second and third transistors are mutually connected and are grounded directly, or of through a resister or a diode that is formed by mutually connecting a gate and a source. Gates of the above-described first and second transistors constitute an input pair, to which the differential voltage is inputted. The gate and drain of the above-described third transistor are mutually connected. Furthermore, the above-described first, second and third transistors are mutually connected at their drains, and are driven by a constant current. The fourth transistor whose gate is mutually connected to the gate of the above-described first transistor, a fifth transistor whose gate is mutually connected to the gate of the above-described second transistor, and six and seventh transistors whose gates are mutually connected to the gate of the above-described third transistor are mutually connected at their sources and are driven by a constant current. Drains of the above-described fourth transistor and above-described sixth transistor are mutually connected and form one of a differential output pair. Drains of the above-described fifth transistor and above-described seventh transistor are mutually connected, and form the other of the differential output pair. Then, each gate ratio (W/L) of the above-described sixth and seventh transistors is a half of a gate ratio (W/L) of the above-described third transistor.
Alternatively, the MOS linear transconductance amplifier comprises first, second, third and forth transistors whose sources are mutually connected, and which are driven by the constant current. The common voltage of the differential input voltage is applied to the gate of the above-described first transistor. Gates of the above-described second and third transistors constitute an input pair, to which the differential voltage is inputted. The gate and drain of the above-described fourth transistor are mutually connected. Furthermore, the above-described second, third and fourth transistors are mutually connected at their drains, and are driven by the constant current. A fifth transistor whose gate is mutually connected to the gate of the above-described second transistor, a sixth transistor whose gate is mutually connected to the gate of the above-described third transistor, seventh and eighth transistors whose gates are mutually connected to the gate of the fourth transistor are mutually connected at their sources and are driven by a constant current. Drains of the above-described fifth transistor and above-described seventh transistor are mutually connected and form one of the differential output pair. Drains of the above-described sixth transistor and above-described eighth transistor are mutually connected, and form the other of the differential output pair. In addition, each gate ratio (W/L) of the above-described seventh and eighth transistors is a half of the gate ratio (W/L) of the above-described fourth transistor.
The MOS linear transconductance amplifier including a current mirror circuit, wherein the current flowing in the above-described first transistor is the reference current, currents having predetermined mirror ratios are supplied to the common drain of the above-described second, third and fourth transistors, and one and the other of the above-described differential output pair, respectively.
Next, with changing words, an operation of the MOS linear transconductance amplifier according to the present invention will be described once again. As a method of obtaining a straight line from a curve with the square-law characteristics is generally called a parabolic characteristics, there is a method of using a class A operation obtained by adding square characteristics to the parabolic characteristics besides a class AB operation obtained by reducing the parabolic characteristics from the parabolic characteristics. Since it is possible to configure a circuit without including a p-channel transistor on a signal path in case of current addition procedure, improvement in its frequency characteristic can be estimated.